Codegen: vector lowering + cost model + diagnostic

Goal

Lower eligible loops to SIMD and make the guarantee diagnosable.

Implementation Sketch

Lower to simd_* vector body + scalar tail in ori_llvm reusing the Intrinsics lowering; one lowering reached by auto + manual paths. Cost model vetoes only when scalar is not slower; #vectorize forces, #no_vectorize opts out. ori explain --vectorization reports gate-pass + veto reason.

Spec References

Proposal §5 cost-model veto; §6 one lowering two paths; intrinsics-v2 register-allocation guarantee.

Work Items

• Lower eligible loops (element-wise map/zip + reorder-safe reductions) to a simd_* vector body + scalar tail in ori_llvm, reusing the Intrinsics lowering (one lowering, two entry paths).
• Implement the cost model (veto only when the scalar form is demonstrably not slower); honor #vectorize (force past veto, still gate-checked) and #no_vectorize (opt out).
• Implement ori explain --vectorization <fn>: report that a loop passed the gate and the specific cost-model reason it was not vectorized, so the guarantee is auditable, never silent.