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s03 — Architecture Design + Design-Validation Gate

Goal

The locked, falsifiable design documents for every backend subsystem — BIR, ArchConfig/MIR, regalloc, object/link, tiers — plus a design-validation gate (the aims-burden section-00 pattern) that must PASS before any implementation section starts.

Implementation Sketch

Design docs in content/, decision records for every contested choice; inputs are the s01/s02 dossiers + the plan-creation research (boundary surfaces verified at plan time):

  • BIR design: SoA storage (parallel tags/data arrays + u32 extra pool, per-function instance), block parameters (matching ArcFunction — compiler_repo/compiler/ori_arc/src/ir/mod.rs:387), value model, type references as Idx into the existing Pool, fact side-tables (index-aligned maps; SLOTS reserved now: effects, return-provenance, reuse-events, uniqueness — populated at s18), span provenance through lowering, BIR verifier invariants (use-before-def, block connectivity, RC-op preservation: BIR translation NEVER adds/removes/moves RC ops — AIMS invariant 5).
  • ArchConfig + MIR design: per-arch config (register lists, masks, lower fns), MIR-per-arch shape (SoA again), the wasm virtual-register arch (OnWasmStack flag model), encoder interfaces.
  • Regalloc design: schedule pass contract, liveness, greedy linear scan over u64 masks, spill heuristic, block-param handling (no phi insertion), symbolic checker contract (input: pre/post-alloc MIR; verdict: per-edge value-location consistency).
  • Object/link design: object-crate emission path, minimal relocation set per ISA, wasm module writer, system-linker driving (reuse LinkerFlavor shape from ori_llvm/src/aot/linker/), RuntimeConfig::detect() reuse for libori_rt.a.
  • Tier design: fast tier = BIR -> MIR -> emit with zero mid-end; optimizing tier = mid-end over BIR then same lowering; dev-mode shape decision (quick-AOT vs in-memory) recorded for s22.
  • Design-validation gate: falsifiable criteria — e.g. (1) BIR can represent every ArcInstr/terminator incl. unwind edges without loss (paper-walk all 21+8 variants); (2) fact side-table slots cover every s18 surface field; (3) ABI classification sharable with ori_llvm without circular deps; (4) wasm fits the ArchConfig frame on paper; (5) /tpr-review of the design docs returns clean or all findings cured. Gate FAIL routes back into design, never forward.

Constraints

  • Design docs are plan content, not compiler source; no compiler edits in this section.
  • Every design claim grounded to dossier or verified boundary facts; UNVERIFIED flags resolved before the gate.

Work Items

  • BIR design doc (storage, block params, fact-slot reservation, verifier invariants, RC-op-preservation rule) + decision records.
  • ArchConfig + per-arch MIR + encoder-interface design doc covering all 5 targets incl. the wasm virtual-register model.
  • Regalloc + schedule-pass + symbolic-checker design doc.
  • Object-emission/link strategy doc (relocation set per ISA, wasm module writer, linker driving, runtime discovery reuse).
  • Tier design doc (fast/optimizing boundaries, dev-mode shape decision for s22).
  • Design-validation gate executed: all falsifiable criteria evaluated with artifacts, /tpr-review on the design set clean; PASS recorded before s04 starts.