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s10 — Fast Tier: Full ISel Coverage

Goal

Every ArcInstr variant (21) and ArcTerminator variant (8) lowers through BIR->MIR on every target — the fast tier becomes semantically complete (unwind-edge lowering stubs route to s13; everything else real).

Implementation Sketch

Coverage waves over the instruction surface verified at plan time (ori_arc/src/ir/instr.rs):

  • Data + control: Construct (all CtorKind incl. closures {fn_ptr,env_ptr} per CG:TR-5 16-byte pair), Project (CompiledLayoutPlan field-offset IDs; NEVER hand-computed offsets), Select, Switch (jump tables + compare chains by density), Jump args as block-param moves (parallel-move resolution).
  • Ownership surface: consume exact AIMS logical event/drop-plan identities and project them through CompiledLayoutPlan(TargetSpec). The shipped six-way RcStrategy mapping (HeapPointer/FatPointer/Closure/AggregateFields/ InlineEnum/Iterator), helper calls, header load, recursive field walk, and tag switch are transitional physical mechanisms to preserve, not AIMS vocabulary. IsShared, COW gates, Reset/Reuse/CollectionReuse, and Burden* lowering must preserve the frozen event order and obligations while selecting only plan-admitted instructions/helpers. The backend authors zero logical ownership policy (invariant 5).
  • Apply family: Apply/ApplyIndirect/PartialApply (env construction), Invoke/InvokeIndirect lower their normal edge now with unwind edges stubbed to abort-on-unwind until s13 (explicit todo-with-diagnostic, never silent).
  • Protocol builtins intercepted before call emission: __index, iter, __iter_next, ori_iter_drop, __collect_set (ownership semantics per arc.md protocol table).
  • Niche/narrowing fidelity: enum tag reads/writes through CompiledLayoutPlan encoding entries (niche-encoded layouts honored); integer narrowing uses the shared target storage width with trunc-store/sext-load discipline (RN-4).
  • Per-ISA fan-out: each wave lands x86-64 first, then aarch64/riscv64/s390x/wasm within the same wave (section-local matrix; the wave is not done until all 5 pass).

Test Strategy

  • Matrix (the load-bearing one): instr-family x element type {int, str, [int], Option, closure, struct, map, set} x target — AOT/direct-WASM executed with evaluator/VM/LLVM/native parity assertions; cells tracked in a coverage table in this section.
  • Semantic pins: per logical ValueSemanticsId/ExecutableDropPlanId class, assert exact event preservation plus the target-plan-selected instruction or runtime call (FileCheck-style on disassembly or MIR dump); retain COW three-path pins (static-unique elides check, static-shared skips check, dynamic branches).
  • Negative pins: unwind-edge stub MUST abort with diagnostic (not run past); niche-encoded enum mis-read fixture fails.
  • ORI_CHECK_LEAKS=1 + valgrind on the RC-heavy cells; debug+release green.

Work Items

  • Data+control wave: Construct/Project/Select/Switch/Jump-args lowering on all 5 targets with CompiledLayoutPlan-driven layout and no local classifier.
  • Ownership wave: Rc*/IsShared/Set/SetTag/Reset/Reuse/CollectionReuse/Burden* for every logical ValueSemanticsId/ExecutableDropPlanId class plus every selected CompiledLayoutPlan mechanism on all five targets. Retain the six legacy RcStrategy shapes only as migration-parity coverage, alongside cow_annotations and drop_hints fidelity.
  • Apply wave: Apply/ApplyIndirect/PartialApply + Invoke normal-edge (unwind stub with explicit abort diagnostic) on all 5 targets.
  • Protocol-builtin interception (5 builtins) with ownership-correct emission.
  • Niche + narrowing fidelity (enum reprs, trunc/sext at storage sites) per repr.md rules.
  • Coverage matrix table complete (instr x type x target) with parity green; strategy/COW pins + negative pins landed; leaks/valgrind clean on RC cells.