Multi-Backend Representation Optimization & ARC Intelligence

13 sections

65%
Section 1 Representation IR & Decision Framework Section 2 Transitive Triviality & ARC Elision Section 3 Value Range Analysis Framework Section 4 Integer Narrowing Pipeline Section 5 Float Narrowing Pipeline Section 6 Struct & Tuple Layout Optimization Section 7 Enum Representation Optimization Section 8 Escape Analysis & Physical Placement Section 9 ARC Header Compression Section 10 Thread-Local Non-Atomic ARC Section 11 Collection Specialization Section 12 Verification & Benchmarks Section 13 Shared Representation Evidence and Backend Layout Plans
Overview

Ori programs use compact, fast representations in every executable backend without exposing representation choices to programmers or allowing the backends to rediscover semantic facts independently. This realizes the approved representation-optimization proposal and the parent missions.md §Compiler / §AIMS intent: semantics remain canonical, while layout, allocation, and physical ownership/cleanup costs — including RC traffic when a plan selects counters — become the compiler's problem.

○

In Progress

3 sections
Section 7 In Progress

Enum Representation Optimization

Optimize enum layout with niche filling, discriminant narrowing, tagged pointers, and payload compression — matching Rust's enum layout optimizations

66/130 tasks
Section 11 In Progress

Collection Specialization

Optimize collection representations: SSO, SVO, packed and narrowed storage, and proof-backed in-place mutation for unique collections

1/62 tasks
Section 12 In Progress

Verification & Benchmarks

Prove representation correctness, leak freedom, speed, and memory efficiency across evaluator, VM, LLVM, and ori_backend without backend-local proof or layout drift

0/93 tasks
○

Planned

4 sections
Section 8 Not Started

Escape Analysis & Physical Placement

Compute lifetime/locality once in AIMS, combine it with neutral extent evidence, and let VM or compiled layout choose a satisfying physical placement

0/78 tasks
Section 9 Not Started

ARC Header Compression

Freeze site-keyed owner bounds and ownership-observation events in AIMS, then let VM and compiled layout plans choose independently verified storage and ownership operations

0/43 tasks
Section 10 Not Started

Thread-Local Non-Atomic ARC

Freeze backend-neutral ThreadReachability once in AIMS, then let validated VM and compiled plans choose synchronization that satisfies it

0/49 tasks
Section 13 Not Started

Shared Representation Evidence and Backend Layout Plans

Split representation proof from physical layout, preserve the shipped LLVM path exactly, give LLVM and ori_backend one compiled target-layout contract, and let the VM exploit the same proofs through VM-private safe storage

0/45 tasks
✓

Completed

6 sections
Section 1 Complete

Representation IR & Decision Framework

Deliver the historical ReprPlan/LLVM integration, then preserve its backend-neutral evidence for VmLayoutPlan and CompiledLayoutPlan projections

202/202 tasks
Section 2 Complete

Transitive Triviality & ARC Elision

Classify compound types as trivial when all transitive children are scalar, eliding all ARC operations for these types

102/102 tasks
Section 3 Complete

Value Range Analysis Framework

Build an abstract interpretation engine over integer intervals that computes provable value ranges for every int-typed expression in a function

169/169 tasks
Section 4 Complete

Integer Narrowing Pipeline

Lower int (semantic i64) to the smallest machine integer (i8/i16/i32) that preserves correctness, saving memory in struct fields, collections, and stack slots

108/108 tasks
Section 5 Complete

Float Narrowing Pipeline

Lower float (semantic f64) to f32 when the compiler can prove zero precision loss for the specific values used

74/74 tasks
Section 6 Complete

Struct & Tuple Layout Optimization

Deliver the historical LLVM field-layout optimization, then project shared field identity into distinct VM and compiled physical layouts

67/67 tasks