Gate close — full test-all.sh + intel_repo pytest green
Goal
Verify the fix-completeness gates across both verification surfaces (compiler test-all + intel_repo pytest) before the plan completes.
Implementation Sketch
Two verification surfaces, neither subsumes the other: the compiler-side ./test-all.sh (test-all = compiler-state SSOT) exercises the oric emit-scip Rust crate tests + the emitter under debug + release; the intel_repo pytest exercises the Python/Neo4j importer, HAS_VARIANT extraction, and rust-analyzer ingest paths that ./test-all.sh never touches. Both must be green at close.
Spec References
Fix-completeness layer matrix: layer-coverage.md §1/§2 (every layer covered-or-justified-N/A). test-all = compiler-state SSOT (CLAUDE.md §Test & Doc Disciplines).
Work Items
- Close the plan: full
./test-all.shclean on the compiler side AND the intel_repo pytest gate green covering the SCIP->Neo4j importer + the HAS_VARIANT extraction edge + rust-analyzer ingest. Fix-completeness matrix satisfied per layer-coverage.md with every layer covered-or-justified-N/A; dual-exec parity N/A (compile-time index emitter).
Test Coverage
- L12 Production entry point — COVERED: the gate runs both real verification surfaces end-to-end. Per-section L1..L11 dispositions roll up from sections 00-06 (emitter sections: L1/L2/L12 COVERED, L3-L11 N/A as compile-time index emitter; importer/ingest sections: L12 COVERED via pytest, L1-L11 N/A as Python/Neo4j path). Dual-exec parity (L9) N/A: compile-time index emitter, not an eval-path.